B&B Electronics PC Watchdog Timer Card ATRWDT Bedienungsanleitung PDF herunterladen (Seite 23)

P104-WDG-CSM User Manual

Mode 5: Hardware Triggered Strobe

In this mode, the counter will start counting after the rising edge of the trigger input and will go

low for one clock period when the terminal count is reached. The counter is retriggerable. The

output will go low until the full count after the rising edge of the trigger.

Programming

On the card, the 8254 counters occupy the following addresses:

Base Address Read/Write Counter 0

Base Address +1 Read/Write Counter 1

Base Address +2 Read/Write Counter 2

Base Address +3 Read/Write Counter Control Register

The counters are programmed by writing a control byte into the counter control register. The

control byte specifies the counter to be programmed, the counter mode, the type of read/write

operation, and the modulus. The control byte format is a follows:

B7 B6 B5 B4 B3 B2 B1 B0

SC1 SC0RW1RW0M2M1M0BCD

SC0 and SC1: These bits select the counter that the control byte is destined for.

SC1 SC0 Function

0 0 Program Counter 0

0 1 Program Counter 1

1 0 Program Counter 2

1 1 Read/Write Command

RW0 and RW1: These bits select the read/write mode of the selected counter.

RW1 RW0 Counter Read/Write Function

0 0 Counter Latch Command

0 1 Read/Write LS Byte

1 0 Read/Write MS Byte

1 1 Read/Write LS Byte, then MS Byte

M0, M1, and M2: These bits set the operational mode of the selected counter.

Mode M2 M1 M0

0 0 0 0

1 0 0 1

2 x 1 0

3 x 1 1

4 1 0 0

5 1 0 1

BCD: Set the selected counter to count in binary (0) or BCD (1).

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B&B Electronics PC Watchdog Timer Card ATRWDT Bedienungsanleitung Seite 23